"EA6300V1" (Q87-EA6400) BCM4360

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Fishrman
DD-WRT Novice


Joined: 18 Jun 2007
Posts: 25

PostPosted: Fri Aug 11, 2017 10:06    Post subject: Reply with quote
I have switched on one of them to Merlin.. but that did not give me the port back. Its still broken.
Sometimes the port blinks even though there is no cable inserted.
Sponsor
magic_ninja
DD-WRT Novice


Joined: 14 Jan 2017
Posts: 2

PostPosted: Sat Aug 12, 2017 1:22    Post subject: Reply with quote
I'm trying to update to the 7.5 firmware. I have an EA6400 and I downloaded the 7.5 file for the EA6400. Two questions:

Is this the latest firmware AND
I'm having trouble trying to flash the router, it is telling me it failed and loading the old firmware. I can't quite remember the process for this or how to find it (it has been a year or more since I did the install).
deslatha
DD-WRT User


Joined: 12 Jul 2016
Posts: 187

PostPosted: Wed Aug 16, 2017 10:17    Post subject: How to tweak and improve performance on ea6400 Reply with quote
first of all, ea6400 had :
CPU BCM4708A0 (800Mhz x 2) 
you can check by: cat /proc/cpuinfo
Switch BCM4708A0 Gigabit 
you can check by: cat /proc/pci
it is bcm53011x
Ram 128MB (Hynix H5PS1G63JFR-S6C) 
no way to check but with multimeter it is 1.8v. with data sheet, it is 1gbit, ddrII 800mhz, CL=6 so actually it is 64mb x 8 bank x 16 bit.
Flash 128MB (Spansion S34ML01G100TF100). it is only 8 bit Input/Output 
2.4 GHz BCM43217 2x2 802.11b/g/n with PA but no LNAs so max=25dBm
5GHz BCM4360, RMFD RFFM4501 802.11a/n/ac (x3)  with PA but no LNAs so max=20dBm

ea6400 may have custom ROM inside cpu, so if the cfe does not match then it may lock up WAN and LAN port. change you brick the router. minimum speed is 400mhz and can config to up 1200 mhmz. if temperature show around 70 degree C then you safe to set at 1200mhz, but don’t do in GUI. if you do in GUI interface then it only set clkfreq=1200. no ram bus, so router may be lock it up and got bricked.

ea6400 used Hynix H5PS1G63JFR-S6C with minimum CL=4 up to CL=6 (DDRII).
default set are: clkfreq=800,333 sdram_config=0x146
so you can set by : nvram set clkfreq=1200,400 nvram set sdram_config=0x145

code:
devinfo set clkfreq=1200,400
devinfo set sdram_config=0x145
devinfo commit

now ea6400 can run almost double time faster than before. if you run FW from other router like RT 68u that support to run DDRIII, then change you bricked ae6400 due to FW only see minimum clk=333. Remember that DDRII run at 333, 400, 533 mhm, DDRIII run at 533, 667, 800mhz.

every time a6400 power up, it start from beginning to check default nvram in cfe, a loophole make slow process , so you need bypass make router direct run nvram in mtd1=nvram area, not default nvram in cfe. then:
nvram set sdram_init=0x0400
nvram set sdram_refresh=0x8400
sdram_ncdl=0000
now your ea6400 run flawless.

now depend on you want to run linksys or ddwrt; on linksys there are 1.1.40 r137734 that let you config nvram on channel and txpwr. default eprom set for router, 2 and 5ghz are 8,8,11.
command prompt to tweak :
nvram set sromrev=11
nvram set 0:sromrev=11
nvram set 1:sromrev=11

due to a6400 does not have LNAs ic then max set power transmit=6F. default set for 2 and 5ghz =62,4e,4a. command prompt to tweak:
nvram set 0:maxp2ga0=62
nvram set 0:maxp2ga1=62
nvram set 1:maxp5ga0=62,62,62,62
nvram set 1:maxp5ga1=62,62,62,62
nvram set 1:maxp5ga2=62,62,62,62
now your ea6400 have max its power.

wireless data depend on 3 facts: power distance, mcs index data compressed, channel BW time. for max mcs index by default on 2 and 5ghz=4,6,5,4 command prompt to tweak:
nvram set 0:rxgains2gtrisoa0=7
nvram set 0:rxgains2gtrisoa1=7
nvram set 1:rxgains5ghtrisoa0=7
nvram set 1:rxgains5ghtrisoa1=7
nvram set 1:rxgains5ghtrisoa2=7
nvram set 1:rxgains5gmtrisoa0=7
nvram set 1:rxgains5gmtrisoa1=7
nvram set 1:rxgains5gmtrisoa2=7
nvram set 1:rxgains5gtrisoa0=7
nvram set 1:rxgains5gtrisoa1=7
nvram set 1:rxgains5gtrisoa2=7
now your ea6400 improve perform sendding data.

want used more channel, then here command prompt to tweak:
nvram set 0:ccode=#a
nvram set 0:regrev=#a
with little tweak in telnet that give your ea6400 run like superman fly.
here the stock FW that let you edit nvram.



linux2.bin
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 Filename:  linux2.bin
 Filesize:  29 MB
 Downloaded:  474 Time(s)



Last edited by deslatha on Fri Aug 25, 2017 6:25; edited 1 time in total
Matrix250
DD-WRT Novice


Joined: 23 Aug 2017
Posts: 2

PostPosted: Wed Aug 23, 2017 18:25    Post subject: Works on EA6400 Reply with quote
This is my first post on this site but just wanted to mention that I was able to get DD-WRT working on my EA6400. Although not on the supported list, it works well.

The post from butterworth on Feb 22, 2016 was very helpful. The first few attempts did not work and there are a few methods available, this is what worked for me.

Flash linksys-ea6400-webflash.bin to linux2 and linux
erase nvram
reboot
Afterwards it loaded an open dd-wrt network but could not connect to it and appeared bricked.
I then used the Asus Rescue tool and flashed the super-hacky image which booted sucessfully.
After booting the super-hacky build, I flashed to the full image and all is well.

The power light does not enable by default, adding "gpio enable 8" to the startup script resolves this issue.

Long live DD-WRT!
jwh7
DD-WRT Guru


Joined: 25 Oct 2013
Posts: 2670
Location: Indy

PostPosted: Wed Aug 23, 2017 20:01    Post subject: Re: Works on EA6400 Reply with quote
Matrix250 wrote:
I was able to get DD-WRT working on my EA6400. Although not on the supported list, it works well.
Good to hear; to what 'supported list' do you refer? It is in the Supported Devices wiki.

If you mean the Router Database, don't use that. Please read the Peacock announcement. Smile

_________________
# NAT/SFE/CTF: limited speed w/ DD # Repeater issues # DD-WRT info: FAQ, Builds, Types, Modes, Changes, Demo #
OPNsense x64 5050e ITX|DD: DIR-810L, 2*EA6900@1GHz, R6300v1, RT-N66U@663, WNDR4000@533, E1500@353,
WRT54G{Lv1.1,Sv6}@250
|FreshTomato: F7D8302@532|OpenWRT: F9K1119v1, RT-ACRH13, R6220, WNDR3700v4
deslatha
DD-WRT User


Joined: 12 Jul 2016
Posts: 187

PostPosted: Fri Aug 25, 2017 5:57    Post subject: part 2 setting devinfo and nvram varies config(con’t) Reply with quote
jwh7 wrote:
Matrix250 wrote:
I was able to get DD-WRT working on my EA6400. Although not on the supported list, it works well.
Good to hear; to what 'supported list' do you refer? It is in the Supported Devices wiki.

As you you known that a6400 have so much problem due to first stage on Soc bcm470x series. there are some fault on FW and HW designed. when i look at HW and compare that a6400 and before used ddrII with set as cl=4,cl=5,cl=7.
code:
sdram_config=0x0144 and clkfreq=1200,333
or
sdram_config=0x0145 and clkfreq=1200,400
0r
sdram_config=0x0147and clkfreq=1200,533

for set cl=6 can either sdram clkfreq are 333 or 400 that cpu does not like; special for wireless chipset.

and that time Soc bcm470x series used ARM cortex v7 . i don’t know what max speed but when you look around 2013 , there are many devices used it. like am logic android tv with max 1512mhz, (The Cortex-A9 was introduced in 2007. It features L1 instruction and data caches that can be configured independently to 16, 32 or 64KB; up to 8MB of L2 cache and clock rates as high as 2GHz. )<http://www.tomshardware.com/reviews/router-soc-101,4392.html#p3.
so it should be normal set config at 800,1000,1200;not over clock. you can set higher or lower but most firmware did not setup for… (request Kong if you like). due to use wrong firmware that use chipset ddrIII with set from 667 to 800mhz could brick a6400. and the import thing is unique between cpu and memory. best option is set at even ratio.
code
devinfo show clocks

25mhz : 100mhz : 200mhz :400mhzx2 : 1200mhzx2
oscillator module : clock : bus : sdram : cpu
at this setting a6400 run so well and faster up to 60% than stock or wrong setting with bogomips up to 4800 compare to android tv The G-Box Midnight MX2 that has 6000 score.

due to limited of scram then you should set 2.4ghz with WPA ; not WPA2. 5 ghz has not effected. then tx data go up from 217mbps to 300mbps.

On the HW , PS for ddrII is 1.8v by adjust transistor, not fixed voltage. due to cpu lookup cfe and setting, memory chipset can’t be function normal. as Asus or Netgear used fixed PS to sdram ic, this will made ea6400 lag on timming lantecy on wireless data.

here the stock devinfo file pull out from broken ea6400 and cfe file from upgrade ea6500v2 and tweak if you want improve the router. due to limited of max size of FW setting is 29.5 mb, if any ddwrt bigger than that could soft brick ea6400.



ea6400_upgrade.zip
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 Filename:  ea6400_upgrade.zip
 Filesize:  121.64 KB
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Last edited by deslatha on Fri Aug 25, 2017 6:13; edited 1 time in total
deslatha
DD-WRT User


Joined: 12 Jul 2016
Posts: 187

PostPosted: Fri Aug 25, 2017 6:12    Post subject: Reply with quote
link626 wrote:
How do I revert ea6400 to stock firmware from ddwrt?
.


for someone want go back to stock FW or lost bk. here the omg FW with can reload to original stock with 1 cli when you use ar cfe prompt.

code:
flash -noheader 192.168.1.2:ea6400_stock.bin nflash0


login: admin/admin
it may take up to 10 minutes due tftp32 only trans only around 250kb/s. be patient.



ea6400_stock_tweak.rar
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 Filename:  ea6400_stock_tweak.rar
 Filesize:  26.72 MB
 Downloaded:  245 Time(s)

magic_ninja
DD-WRT Novice


Joined: 14 Jan 2017
Posts: 2

PostPosted: Sat Aug 26, 2017 11:25    Post subject: Reply with quote
I'm having issues with the wifi radio on the Merlin 7.2 firmware. I was wanting to update to the 7.5, but the commands from the guide aren't working in ssh.

Could anyone point me in the right direction to do a firmware upgrade? I've been all-wired until now, so I'm not sure what is happening with the wireless radio. It randomly drops the signal, and every 5-10 pings, the latency will jump up to almost 1second. There are only 3 devices on wireless as well, and I'm out in the country so there aren't any other networks near me that are interfering.

At this point I'm contemplating buying a new router, but would like to try a couple different firmwares on this one first just to make sure it is a hardware issue.
Matrix250
DD-WRT Novice


Joined: 23 Aug 2017
Posts: 2

PostPosted: Sat Aug 26, 2017 17:29    Post subject: Re: Works on EA6400 Reply with quote
jwh7 wrote:
Matrix250 wrote:
I was able to get DD-WRT working on my EA6400. Although not on the supported list, it works well.
Good to hear; to what 'supported list' do you refer? It is in the Supported Devices wiki.

If you mean the Router Database, don't use that. Please read the Peacock announcement. Smile



When you click on the link on the giant supported list page, it reads as follows:

"Linksys EA6400
DD-WRT Install instructions and guide are under development. Please see the forum thread linked below for the current state for this router."

Not much support to be found. The link to this forum was useful though. Thank you team DD-WRT.
link626
DD-WRT Novice


Joined: 19 Feb 2010
Posts: 42

PostPosted: Thu Sep 07, 2017 7:37    Post subject: Reply with quote
I'm thinking about trying ddwrt once again.
Which version is the fastest and most stable?

Last time I loaded it on the ea6400, performance was pretty crap.
But I have old N devices that really need the 40mhz wide band.

The stock linksys fw has been rock solid for me, but stupid linksys won't let me force 40mhz on 2.4ghz.
cheerful
DD-WRT Novice


Joined: 07 Sep 2017
Posts: 3

PostPosted: Thu Sep 07, 2017 8:23    Post subject: Reply with quote
Hi,

I just purchased a Linksys EA6400 to replace a broken Netgear. Just set up with stock firmware and it's working but running quite hot. Looks like people have success putting DD-WRT on it.

Some background. The route is running firmware 1.1.40.172334. I have tried to update its firmware but it says nothing is found. Downloaded EA6400_1.1.40.176337_prod.img from Linksys but the router says it's invalid. I'm not sure if this signal some issues.

This is a very long thread. What's the latest installation instruction for a newbie on DD-WRT?

Thanks
deslatha
DD-WRT User


Joined: 12 Jul 2016
Posts: 187

PostPosted: Thu Sep 07, 2017 17:54    Post subject: Reply with quote
link626 wrote:
I'm thinking about trying ddwrt once again.
Which version is the fastest and most stable.
The stock linksys fw has been rock solid for me, but stupid linksys won't let me force 40mhz on 2.4ghz.


try to stock file i post. it is able unlock all channel and 40 bw mhz . if you know how to flash cfe then here the best cfe for ea6400.
what feature:
*porting cfe from xvortex( able hlod reset button for loading new FW).
* setting clock rate 1200,400 which 75% faster than stock.
*porting 2.4ghz from AC56ac which maximum 27.5 dbm.
*porting 5ghz from r7000 which maximum 25.0 dbm.
*including calibrating radio wifi,ssid,secret code ...etc.
*maximum of FW now 31.75 mB.
*max data by wifi.
* free softbricked from reset 30/30/30.

for best adv. use : dd-wrt.v24-K3_AC_ARM_STD_128K.bin to get maximun nvram.
http://www.desipro.de/ddwrt/K3-AC-Arm/
notes: if you use VPN then setting :clkfreq=1400,533. sdram_config=0x0147.
for running stock FW , you need replace all parameter from this cfe to stock cfe.



cfe_ea6400_OC.bin
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 Filename:  cfe_ea6400_OC.bin
 Filesize:  512 KB
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deslatha
DD-WRT User


Joined: 12 Jul 2016
Posts: 187

PostPosted: Thu Sep 07, 2017 18:01    Post subject: testing on cpu Reply with quote
Here the testing of cpu of ea6400 base on Soc 4708Axx. result that a FW have default setting which max clock rate 700mhz and minimum 300mhz.
root@DD-WRT:~# cat /proc/dmu/temperature
625
root@DD-WRT:~#
root@DD-WRT:~# cat /proc/cpuinfo
model name : ARMv7 Processor rev 0 (v7l)
processor : 0
BogoMIPS : 2786.91
Features : half fastmult edsp tls
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x3
CPU part : 0xc09
CPU revision : 0

model name : ARMv7 Processor rev 0 (v7l)
processor : 1
BogoMIPS : 2786.91
Features : half fastmult edsp tls
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x3
CPU part : 0xc09
CPU revision : 0

Hardware : Northstar Prototype
Revision : 0000
Serial : 0000000000000000
root@DD-WRT:~#
root@DD-WRT:~# wl -i eth1 txpwr_target_max
Maximum Tx Power Target (chanspec:0x1006): 27.50 27.50
root@DD-WRT:~#
root@DD-WRT:~# wl -i eth2 txpwr_target_max
Maximum Tx Power Target (chanspec:0xd024): 25.00 25.00 25.00
Init Arena
Init Devs.
Boot partition size = 262144(0x40000)
DDR Clock: 400 MHz
Info: DDR frequency set from clkfreq=1400,*400*
et0: Broadcom BCM47XX 10/100/1000 Mbps Ethernet Controller 6.39.163.39 (r394801)
CPU type 0x0: 1400MHz
Tot mem: 131072 KBytes

CFE mem: 0x00F00000 - 0x0109DF6C (1695596)
Data: 0x00F56650 - 0x00F56B18 (1224)
BSS: 0x00F56B28 - 0x00F9BF6C (283716)
Heap: 0x00F9BF6C - 0x0109BF6C (1048576)
Stack: 0x0109BF6C - 0x0109DF6C (8192)
Text: 0x00F00000 - 0x00F4B224 (307748)
Boot: 0x0109E000 - 0x010DE000
Reloc: I:00000000 - D:00000000

Boot version: v2.1.10
NR_IRQS:256
MPCORE GIC init
soc_dmu_init
add clk lookups
MPCORE Global Timer Clock 700000000Hz on IRQ 27
sched_clock: 32 bits at 700MHz, resolution 1ns, wraps every 3067833343ns
clocksource: mpcore_gtimer: mask: 0xffffffffffffffff max_cycles: 0xa17102bcf3, max_idle_ns: 440795224838 ns
register local timer
smp_twd: clock not found -2
Calibrating local timer... 699.45MHz.
Calibrating delay loop... 2786.91 BogoMIPS (lpj=13934592)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
2 cores has been found
Setting up static identity map for 0x85e0 - 0x8614
L2C: platform provided aux values permit register corruption.
L2C: DT/platform modifies aux control register: 0x0a130000 -> 0x7a530000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 16 ways, 256 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x4e530001
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
Brought up 2 CPUs
SMP: Total of 2 processors activated (5573.83 BogoMIPS).
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
futex hash table entries: 512 (order: 3, 32768 bytes)
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
coherence_win_size = 10000000
coherence_flag = FFFFFFF8
ddr_phys_offset_va =FFFFFFFF
ddr_phys_offset2_va =A8000000

***********************************************************
Init Arena
Init Devs.
Boot partition size = 262144(0x40000)
DDR Clock: 400 MHz
Info: DDR frequency set from clkfreq=1200,*400*
et0: Broadcom BCM47XX 10/100/1000 Mbps Ethernet Controller 6.39.163.39 (r394801)
CPU type 0x0: 1200MHz
Tot mem: 131072 KBytes

CFE mem: 0x00F00000 - 0x0109DF6C (1695596)
Data: 0x00F56650 - 0x00F56B18 (1224)
BSS: 0x00F56B28 - 0x00F9BF6C (283716)
Heap: 0x00F9BF6C - 0x0109BF6C (1048576)
Stack: 0x0109BF6C - 0x0109DF6C (8192)
Text: 0x00F00000 - 0x00F4B224 (307748)
Boot: 0x0109E000 - 0x010DE000
Reloc: I:00000000 - D:00000000

Boot version: v2.1.10
NR_IRQS:256
MPCORE GIC init
soc_dmu_init
add clk lookups
MPCORE Global Timer Clock 600000000Hz on IRQ 27
sched_clock: 32 bits at 600MHz, resolution 1ns, wraps every 3579139583ns
clocksource: mpcore_gtimer: mask: 0xffffffffffffffff max_cycles: 0x8a60dd94a9, max_idle_ns: 440795233082 ns
register local timer
smp_twd: clock not found -2
Calibrating local timer... 599.51MHz.
Calibrating delay loop... 2387.14 BogoMIPS (lpj=11935744)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
2 cores has been found
Setting up static identity map for 0x85e0 - 0x8614
L2C: platform provided aux values permit register corruption.
L2C: DT/platform modifies aux control register: 0x0a130000 -> 0x7a530000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 16 ways, 256 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x4e530001
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
Brought up 2 CPUs
SMP: Total of 2 processors activated (4774.29 BogoMIPS).
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns

***********************************************************************
Init Arena
Init Devs.
Boot partition size = 262144(0x40000)
DDR Clock: 400 MHz
Info: DDR frequency set from clkfreq=1000,*400*
et0: Broadcom BCM47XX 10/100/1000 Mbps Ethernet Controller 6.39.163.39 (r394801)
CPU type 0x0: 1000MHz
Tot mem: 131072 KBytes

CFE mem: 0x00F00000 - 0x0109DF6C (1695596)
Data: 0x00F56650 - 0x00F56B18 (1224)
BSS: 0x00F56B28 - 0x00F9BF6C (283716)
Heap: 0x00F9BF6C - 0x0109BF6C (1048576)
Stack: 0x0109BF6C - 0x0109DF6C (8192)
Text: 0x00F00000 - 0x00F4B224 (307748)
Boot: 0x0109E000 - 0x010DE000
Reloc: I:00000000 - D:00000000

Boot version: v2.1.10
NR_IRQS:256
MPCORE GIC init
soc_dmu_init
add clk lookups
MPCORE Global Timer Clock 500000000Hz on IRQ 27
sched_clock: 32 bits at 500MHz, resolution 2ns, wraps every 4294967295ns
clocksource: mpcore_gtimer: mask: 0xffffffffffffffff max_cycles: 0xe6a171a037, max_idle_ns: 881590485102 ns
register local timer
smp_twd: clock not found -2
Calibrating local timer... 499.59MHz.
Calibrating delay loop... 1987.37 BogoMIPS (lpj=9936896)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
2 cores has been found
Setting up static identity map for 0x85e0 - 0x8614
L2C: platform provided aux values permit register corruption.
L2C: DT/platform modifies aux control register: 0x0a130000 -> 0x7a530000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 16 ways, 256 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x4e530001
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
Brought up 2 CPUs
SMP: Total of 2 processors activated (3981.31 BogoMIPS).
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns


***************************************************************
Init Arena
Init Devs.
Boot partition size = 262144(0x40000)
DDR Clock: 400 MHz
Info: DDR frequency set from clkfreq=800,*400*
et0: Broadcom BCM47XX 10/100/1000 Mbps Ethernet Controller 6.39.163.39 (r394801)
CPU type 0x0: 800MHz
Tot mem: 131072 KBytes

CFE mem: 0x00F00000 - 0x0109DF6C (1695596)
Data: 0x00F56650 - 0x00F56B18 (1224)
BSS: 0x00F56B28 - 0x00F9BF6C (283716)
Heap: 0x00F9BF6C - 0x0109BF6C (1048576)
Stack: 0x0109BF6C - 0x0109DF6C (8192)
Text: 0x00F00000 - 0x00F4B224 (307748)
Boot: 0x0109E000 - 0x010DE000
Reloc: I:00000000 - D:00000000

Boot version: v2.1.10
NR_IRQS:256
MPCORE GIC init
soc_dmu_init
add clk lookups
MPCORE Global Timer Clock 400000000Hz on IRQ 27
sched_clock: 32 bits at 400MHz, resolution 2ns, wraps every 5368709118ns
clocksource: mpcore_gtimer: mask: 0xffffffffffffffff max_cycles: 0x5c4093a7d1, max_idle_ns: 440795210635 ns
register local timer
smp_twd: clock not found -2
Calibrating local timer... 399.68MHz.
Calibrating delay loop... 1594.16 BogoMIPS (lpj=7970816)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
2 cores has been found
Setting up static identity map for 0x85e0 - 0x8614
L2C: platform provided aux values permit register corruption.
L2C: DT/platform modifies aux control register: 0x0a130000 -> 0x7a530000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 16 ways, 256 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x4e530001
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
Brought up 2 CPUs
SMP: Total of 2 processors activated (3188.32 BogoMIPS).
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns

**************************************************************************

Init Arena
Init Devs.
Boot partition size = 262144(0x40000)
DDR Clock: 400 MHz
Info: DDR frequency set from clkfreq=600,*400*
et0: Broadcom BCM47XX 10/100/1000 Mbps Ethernet Controller 6.39.163.39 (r394801)
CPU type 0x0: 600MHz
Tot mem: 131072 KBytes

CFE mem: 0x00F00000 - 0x0109DF6C (1695596)
Data: 0x00F56650 - 0x00F56B18 (1224)
BSS: 0x00F56B28 - 0x00F9BF6C (283716)
Heap: 0x00F9BF6C - 0x0109BF6C (1048576)
Stack: 0x0109BF6C - 0x0109DF6C (8192)
Text: 0x00F00000 - 0x00F4B224 (307748)
Boot: 0x0109E000 - 0x010DE000
Reloc: I:00000000 - D:00000000

Boot version: v2.1.10
NR_IRQS:256
MPCORE GIC init
soc_dmu_init
add clk lookups
MPCORE Global Timer Clock 300000000Hz on IRQ 27
sched_clock: 32 bits at 300MHz, resolution 3ns, wraps every 7158278654ns
clocksource: mpcore_gtimer: mask: 0xffffffffffffffff max_cycles: 0x45306eca54, max_idle_ns: 440795215369 ns
register local timer
smp_twd: clock not found -2
Calibrating local timer... 299.75MHz.
Calibrating delay loop... 1196.85 BogoMIPS (lpj=5984256)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
2 cores has been found
Setting up static identity map for 0x85e0 - 0x8614
L2C: platform provided aux values permit register corruption.
L2C: DT/platform modifies aux control register: 0x0a130000 -> 0x7a530000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 16 ways, 256 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x4e530001
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
Brought up 2 CPUs
SMP: Total of 2 processors activated (2393.70 BogoMIPS).
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
***************************************************************************

Init Arena
Init Devs.
Boot partition size = 262144(0x40000)
DDR Clock: 400 MHz
Info: DDR frequency set from clkfreq=400,*400*
et0: Broadcom BCM47XX 10/100/1000 Mbps Ethernet Controller 6.39.163.39 (r394801)
CPU type 0x0: 600MHz
Tot mem: 131072 KBytes

CFE mem: 0x00F00000 - 0x0109DF6C (1695596)
Data: 0x00F56650 - 0x00F56B18 (1224)
BSS: 0x00F56B28 - 0x00F9BF6C (283716)
Heap: 0x00F9BF6C - 0x0109BF6C (1048576)
Stack: 0x0109BF6C - 0x0109DF6C (8192)
Text: 0x00F00000 - 0x00F4B224 (307748)
Boot: 0x0109E000 - 0x010DE000
Reloc: I:00000000 - D:00000000

Boot version: v2.1.10
NR_IRQS:256
MPCORE GIC init
soc_dmu_init
add clk lookups
MPCORE Global Timer Clock 300000000Hz on IRQ 27
sched_clock: 32 bits at 300MHz, resolution 3ns, wraps every 7158278654ns
clocksource: mpcore_gtimer: mask: 0xffffffffffffffff max_cycles: 0x45306eca54, max_idle_ns: 440795215369 ns
register local timer
smp_twd: clock not found -2
Calibrating local timer... 299.75MHz.
Calibrating delay loop... 1196.85 BogoMIPS (lpj=5984256)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
2 cores has been found
Setting up static identity map for 0x85e0 - 0x8614
L2C: platform provided aux values permit register corruption.
L2C: DT/platform modifies aux control register: 0x0a130000 -> 0x7a530000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 16 ways, 256 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x4e530001
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
Brought up 2 CPUs
SMP: Total of 2 processors activated (2393.70 BogoMIPS).
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
*****************************************************************************
Init Arena
Init Devs.
Boot partition size = 262144(0x40000)
DDR Clock: 400 MHz
Info: DDR frequency set from clkfreq=200,*400*
et0: Broadcom BCM47XX 10/100/1000 Mbps Ethernet Controller 6.39.163.39 (r394801)
CPU type 0x0: 600MHz
Tot mem: 131072 KBytes

CFE mem: 0x00F00000 - 0x0109DF6C (1695596)
Data: 0x00F56650 - 0x00F56B18 (1224)
BSS: 0x00F56B28 - 0x00F9BF6C (283716)
Heap: 0x00F9BF6C - 0x0109BF6C (1048576)
Stack: 0x0109BF6C - 0x0109DF6C (8192)
Text: 0x00F00000 - 0x00F4B224 (307748)
Boot: 0x0109E000 - 0x010DE000
Reloc: I:00000000 - D:00000000

Boot version: v2.1.10
NR_IRQS:256
MPCORE GIC init
soc_dmu_init
add clk lookups
MPCORE Global Timer Clock 300000000Hz on IRQ 27
sched_clock: 32 bits at 300MHz, resolution 3ns, wraps every 7158278654ns
clocksource: mpcore_gtimer: mask: 0xffffffffffffffff max_cycles: 0x45306eca54, max_idle_ns: 440795215369 ns
register local timer
smp_twd: clock not found -2
Calibrating local timer... 299.74MHz.
Calibrating delay loop... 1196.85 BogoMIPS (lpj=5984256)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
2 cores has been found
Setting up static identity map for 0x85e0 - 0x8614
L2C: platform provided aux values permit register corruption.
L2C: DT/platform modifies aux control register: 0x0a130000 -> 0x7a530000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 16 ways, 256 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x4e530001
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
Brought up 2 CPUs
SMP: Total of 2 processors activated (2393.70 BogoMIPS).
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
***********************************************************************

at minimum cpu clock speed :
wl -i eth1 txpwr_target_max
Maximum Tx Power Target (chanspec:0x1006): 27.50 27.50
root@DD-WRT:~#
root@DD-WRT:~# wl -i eth2 txpwr_target_max
Maximum Tx Power Target (chanspec:0xd024): 14.00 14.00 14.00
root@DD-WRT:~# nvram get clkfreq
200,400
root@DD-WRT:~# cat /proc/dmu/temperature
647
root@DD-WRT:~# cat /proc/cpuinfo
model name : ARMv7 Processor rev 0 (v7l)
processor : 0
BogoMIPS : 1196.85
Features : half fastmult edsp tls
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x3
CPU part : 0xc09
CPU revision : 0

model name : ARMv7 Processor rev 0 (v7l)
processor : 1
BogoMIPS : 1196.85
Features : half fastmult edsp tls
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x3
CPU part : 0xc09
CPU revision : 0

Hardware : Northstar Prototype
Revision : 0000
Serial : 0000000000000000
root@DD-WRT:~#
***********************************************
each testing runing 24/24 for 72hours and each hour reset and reboot.
cheerful
DD-WRT Novice


Joined: 07 Sep 2017
Posts: 3

PostPosted: Fri Sep 08, 2017 17:51    Post subject: Reply with quote
What are the main features gained with the DD-WRT firmware over stock?
link626
DD-WRT Novice


Joined: 19 Feb 2010
Posts: 42

PostPosted: Sat Sep 09, 2017 7:41    Post subject: Reply with quote
deslatha wrote:
]

try to stock file i post. it is able unlock all channel and 40 bw mhz . if you know how to flash cfe then here the best cfe for ea6400.
what feature:
*porting cfe from xvortex( able hlod reset button for loading new FW).
* setting clock rate 1200,400 which 75% faster than stock.
*porting 2.4ghz from AC56ac which maximum 27.5 dbm.
*porting 5ghz from r7000 which maximum 25.0 dbm.
*including calibrating radio wifi,ssid,secret code ...etc.
*maximum of FW now 31.75 mB.
*max data by wifi.
* free softbricked from reset 30/30/30.

for best adv. use : dd-wrt.v24-K3_AC_ARM_STD_128K.bin to get maximun nvram.
http://www.desipro.de/ddwrt/K3-AC-Arm/
notes: if you use VPN then setting :clkfreq=1400,533. sdram_config=0x0147.
for running stock FW , you need replace all parameter from this cfe to stock cfe.




So, you're saying I can run stock Linksys firmware and manually choose 40mhz?

Can you hack the stock firmware to choose 40mhz ?

All I care about is unlocking 40mhz on 2.4ghz on stock fw.

I don't want to overclock anything.



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